Learn VHDL in Seattle, Washington

This 5 day hands on course presents the elements of the VHDL language (with an emphasis on synthesizable features). It concentrates on the language structures of VHDL. The class is very lab intensive with a minimum of 50% of the time spent on lab exercises. These exercises are a combination of small exercises reinforcing the topics in the lecture, and longer exercises that allow the student to work on “real world�?problems.
Day One
VHDL Design Flow
Design Units �?Entities, Architecture, Packages
Data Types & Math, Logic, Relational Operators
Vectors
Concurrent/Sequential Statements
Combinatorial & Clocked Processes
Hierarchy & Structural VHDL
Introduction to Testbenches

Day Two
Review of Fundamental VHDL Concepts
Vector Operations & Advanced Manipulation
Tri-States & Bi-directional Signals
VHDL Processes �?Advanced Topics
Design Re-use �?Generics
Device Specific Coding
IEEE Library
Testing Clocked Circuits

Day Three
Synchronous Designs
Variables, Packages , & Subprograms
State Machines
Device Specific Coding
Post Synthesis Simulation
Synthesizing Don’t Cares
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The SystemVision VHDL-AMS Modeling course was developed to help you develop VHDL-AMS simulation models for your electrical and mechatronic systems. In this course, you will gain proficiency in analog, digital, mixed analog/digital (mixed-signal), and mixed-technology (multi-physics) model building. You will also learn how to simplify model development with the SystemVision Model Generation Tool, which does much of the modeling work for you. In addition, you will learn how to create and modify symbols for your models.

Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive modeling experience under the guidance of our industry expert instructors.

You will learn how to
Create electrical analog modelsCreate electrical digital modelsCreate electrical mixed-signal modelsCreate mixed-technology (multi-physics) modelsDefine custom models types and functionsDefine custom library packages to promote mode re-useUse the Model Generation ToolIntegrate individual models into a simulatable “system model”Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience devel... [Read More]

This class teaches you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lecture takes you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior.

Hands-on lab exercises will reinforce lecture and discussion topics un the guidance of our industry expert instructors.

You will learn how to
Set up libraries to hold your designs Model hierarchy and connectivity using block diagrams and IBD Model finite state machines with state diagrams Model sequential processes with flow charts Model combinatorial circuits with truth tables Create and edit component symbols Generate HDL for your graphical/textual design Compile your design for simulation Simulate your design using ModelSim® Animate and debug your design Reuse components Convert existing HDL designs into graphical/textual HDL Designer Series designs Create test benches Manage your design using version management Ensure your design meets required design rules using DesignChecker Interface with a wide range of downstream tools (compilers, simulators,... [Read More]

In this 3 day class the designer will learn the basics of the VHDL-AMS (IEEE 1076.1) hardware descriptor language and its efficient use for model creation, validation, and design reuse. The class is intended for analog, mixed-signal, and mixed-nature designers who want to discover what advantages high-level modeling brings to the design process. The three days of the class are spent on the basics of the VHDL-AMS language and teaching efficient modeling practices.
You will learn how to
This class will help designers quickly harness the potential of abstract analog and mixed-signal modeling while avoiding the problems and pitfalls of the new technology. The designer will learn the following skills:

How to code models using the VHDL-AMS notation How to develop efficient mathematical models for encoding with VHDL-AMS How to verify and test continuous, discrete event, and mixed signal models How to write portable, reusable VHDL-AMS code. Upon completion of the training class, the designer will have a good working knowledge of the VHDL-AMS language including its application to the modeling and simulation of analog, mixed-signal, and mixed-discipline circuits and ... [Read More]

RapidGain�?VHDL Using Xilinx is unique in offering delegates experience of the whole FPGA design flow, from VHDL coding and simulation through to downloading a design to a real device, all in a single day. Tightly focused and practical, this one-day hands-on training event will show new and prospective users how to get started with VHDL and Xilinx FPGAs.

Delegates will rapidly gain an understanding of the tools and processes involved in creating an FPGA design, achieving significant initial productivity gains. You will:

Understand the basic structure of Xilinx FPGAs
See how VHDL is used to capture and simulate your FPGA design
Implement a design, step by step, in the Xilinx ISE environment
Download and test your design on a Spartan 3E development board

RapidGain�?VHDL Using Xilinx is not available for in-house delivery.

Who should attend?
Digital designers thinking about making the first moves to VHDL and FPGA design
Managers who want to understand more about the process of creating FPGA designs and VHDL
Analogue or Systems designers who work with digital design teams

Prerequisites
No prior experience of VH... [Read More]

RapidGain�?VHDL Using Lattice is unique in offering delegates experience of the whole FPGA design flow, from VHDL coding and simulation through to downloading a design to a real device, all in a single day. Tightly focused and practical, this one-day hands-on training event will show new and prospective users how to get started wth VHDL and Lattice FPGAs.

Delegates will rapidly gain an understanding of the tools and processes involved in creating an FPGA design, achieving significant initial productivity gains. You will:

Understand the basic structure of Lattice FPGAs
Learn how VHDL is used to capture and simulate your FPGA design
See how the Lattice ispLever software implements your design, step by step
Program the FPGA on a development board

RapidGain�?VHDL Using Lattice is not available for in-house delivery.
Who should attend?
Digital designers thinking about making the first moves to VHDL and FPGA design
Managers who want to understand more about the process of creating FPGA designs and VHDL
Analogue or Systems designers who work with digital design teams

Prerequisites
No prior experience of VHDL or Lattic... [Read More]

RapidGain�?VHDL Using Altera is unique in offering delegates experience of the whole FPGA design flow, from VHDL coding and simulation through to downloading a design to a real device, all in a single day. Tightly focused and practical, this one-day hands-on training event will show new and prospective users how to get started wth VHDL and Altera FPGAs.

Delegates will rapidly gain an understanding of the tools and processes involved in creating an FPGA design, achieving significant initial productivity gains. You will:

Understand the basic structure of Altera FPGAs
Learn how VHDL is used to capture and simulate your FPGA design
See how the Altera Quartus II software implements your design, step by step
Program the FPGA on a development board

RapidGain�?VHDL Using Altera is not available for in-house delivery.
Who should attend?
Digital designers thinking about making the first moves to VHDL and FPGA design
Managers who want to understand more about the process of creating FPGA designs and VHDL
Analogue or Systems designers who work with digital design teams

Prerequisites
No prior experience of VHDL or Altera FP... [Read More]

Expert VHDL Verification is an intensive advanced application class. It teaches engineers how to increase productivity by enhancing their VHDL coding and application skills. The syllabus focuses on test benches and ‘hot�?techniques for verification such as scoreboarding and Transaction Level Verification (TLV).

Carefully designed workshops comprise 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.

Expert VHDL Verification forms the last 3 days of the 5-day Doulos Expert VHDL class.

Who should attend?
Design engineers and verification engineers involved in VHDL test bench development or behavioural modelling for the purpose of functional verification

What will you learn?
A set of VHDL language features that go beyond what is taught on a basic training class
The principles and details of how to approach the problem of design verification using VHDL
How to structure and write large and complex VHDL test benches
The principles and details of how to write behavioural models of hardware components in VHDL
A deeper understanding of the... [Read More]

Fast-track Verilog for VHDL Users is an intensive 2-day conversion-training course teaching the application of the Verilog® Hardware Description Language for programmable logic and ASIC design. It is not suitable for engineers who haven’t already attended the Comprehensive VHDL course or are not well practised in VHDL based design.

By emphasising the similarities and highlighting the differences between the VHDL and Verilog languages and the associated design flows, this course fast-tracks delegates through the Verilog learning curve. It is designed to enable VHDL based engineers to be Verilog-ready for transition to SystemVerilog application. (Check out scheduling and packaging options with SystemVerilog for Design Groups, Comprehensive SystemVerilog and Modular SystemVerilog.)

For other onsite team based training requirements, course content, scope and duration will be customised to the best fit for the specific customer context. Contact Doulos to discuss directly.

The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools. A number of supplementary topics are al... [Read More]

VHDL-AMS Workshop is a comprehensive 4-day class covering the extension to VHDL for analogue and mixed-signal modelling, as well as the underpinning VHDL knowledge required. It includes VHDL-AMS language features, with examples of electronic circuits and systems, and new constructs are explained with reference to circuit simulation algorithms.

The first 2-days of the class examine the VHDL language essentials; coding for register transfer level writing test benches, using VHDL tools and the VHDL design flow. Engineers already proficient in VHDL can omit the ’Introduction to VHDL’ module and attend just the last 2-days.

The course is split between interactive classroom-style lectures and practical hands-on exercises using a commercial simulation tool. The workshops are carefully designed to reinforce the material presented, and illustrate the scope of the language, with interesting exercises.

Who should attend?
Engineers who wish to extend their knowledge of VHDL to the modeling of analogue and mixed-signal electronic circuits.

What will you learn?
The essential syntax and semantics of the VHDL language
How to write VHDL ... [Read More]